Renesas Electronics /R7FA6M1AD /SCI0 /SSR_FIFO

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Interpret as SSR_FIFO

7 43 0 0 00 0 0 0 0 0 0 0 0 (0)DR 0 (Reserved)Reserved 0 (0)TEND 0 (0)PER 0 (0)FER 0 (0)ORER 0 (0)RDF 0 (0)TDFE

PER=0, FER=0, DR=0, TEND=0, TDFE=0, ORER=0, RDF=0

Description

Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)

Fields

DR

Receive Data Ready flag (Valid only in asynchronous mode(including multi-processor) and FIFO selected)

0 (0): Receiving is in progress, or no received data has remained in FRDR after normally completed receiving.(receive FIFO is empty)

1 (1): Next receive data has not been received for a period after normal completed receiving, , when data is stored in FIFO to equal or less than receive triggering number.

Reserved

This bit is read as 0. The write value should be 0.

TEND

Transmit End Flag

0 (0): A character is being transmitted.

1 (1): Character transfer has been completed.

PER

Parity Error Flag

0 (0): No parity error occurred.

1 (1): A parity error has occurred.

FER

Framing Error Flag

0 (0): No framing error occurred.

1 (1): A framing error has occurred.

ORER

Overrun Error Flag

0 (0): No overrun error occurred

1 (1): An overrun error has occurred

RDF

Receive FIFO data full flag

0 (0): The quantity of receive data written in FRDR falls below the specified receive triggering number.

1 (1): The quantity of receive data written in FRDR is equal to or greater than the specified receive triggering number.

TDFE

Transmit FIFO data empty flag

0 (0): The quantity of transmit data written in FTDR exceeds the specified transmit triggering number.

1 (1): The quantity of transmit data written in FTDR is equal to or less than the specified transmit triggering number

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